Backend metallization method and device obtained therefrom

ABSTRACT

A semiconductor device and a method of making it are described. During the formation of the semiconductor device, a hard mask is formed of an etch-resistant material. The mask prevents etchant from etching an area within a dielectric material near a conductive plug. The mask may be formed of a nitride. Conductive material is then deposited withinan etched via and is contacted with the conductive plug.

FIELD OF THE INVENTION

The present invention relates to the fabrication of semiconductordevices. More particularly, the present invention relates to the backendmetatlization process used in the formation of semiconductor devices.

BACKGROUND OF THE INVENTION

There are a variety of semiconductor device types, one particularsemiconductor device being a semiconductor memory device, such as randomaccess memory (RAM) device. Known types of RAM devices include staticrandom access memory (SRAM) devices and dynamic random access memory(DRAM) devices. A DRAM device contains an array of individual memorycells. Each cell includes an integrated circuit on a substrate andconductive material for electrically connecting the cell to otherstructures of a memory circuit.

With reference to FIG. 1, one conventional method for depositingconductive material for backend metallization, is a single Damascenemethod. FIG. 1 shows a simplified single Damascene method for forming ametallization connection to a substrate. It includes depositing anon-conductive layer of material 20, e.g. borophosphosilicate glass(BPSG), on a substrate 24 and pattern etching an opening within thematerial 20. A conductor, e.g. a metal or a doped polysilicon isdeposited over the material 20, thereby filling in the opening andproviding a covering layer on the material 20. Chemical-mechanicalpolishing of the conductor removes the layer of conductor on thematerial 20, leaving a conductive plug M₁. The conductive plug M₁ ispositioned on a doped region 22 provided in the substrate 24. Anadditional layer of non-conducting material 20, e.g. BPSG, is thendeposited over the conductive plug M₁ and the previously depositedmaterial 20. A via 21 is then etched in the material 20 above theconductive plug M₁. A conductive barrier material 12 is then depositedwithin the via 21 and over the additional material 20. Then anotherconductive layer 16 is deposited over the barrier layer 12, therebycompleting an electrical connection between conductive layer 16 anddoped region 20.

Vias 21 may be formed with a positive overlap (the conductive plug M₁ isof to a greater diameter than the via 21), a zero overlap (theconductive plug M₁ and the via 21 are the same diameter), or a negativeoverlap (the conductive plug M₁ has a smaller diameter than the via 21).In FIG. 1, a negative overlap is shown. Because of the decreasing sizesof semiconductor devices, zero overlaps and negative overlaps arebecoming more prevalent.

The conductive layers 12, 16 may be formed of any suitable conductivematerial, such as aluminum, copper or a highly doped polysilicon. Thematerial 20 is preferably formed of a non-conductive material which isrelatively easily removed in a chemical-mechanical polishing or etchingprocess. Most preferably, and as noted, the material 20 is a dopedsilicate glass, such as, for example, BPSG.

In addition to the single Damascene method described above, a doubleDamascene method may be used to form a conductive connection. A doubleDamascene method for forming trench capacitors is described in“Dual-Damascene Challenges Dielectric Etch,” SemiconductorInternational, p. 68-72, August 1999.

One disadvantage associated with the above-described fabrication methodis that sometimes the etched via 21 in the material 20 is offsetslightly relative to the plug M₁, as shown in FIG. 2. This most usuallyoccurs in zero overlap and/or negative overlap fabrication processes.The etching of such an offset via 21 creates an offset opening portion25 along the side of the conductive plug M₁, which during the subsequentlayering of the conductive layers 12, 16 may form an air gap 26 (FIG.2). Initially, the air gap 26 is relatively small, but as the conductivelayers are deposited at elevated temperatures, the gas trapped in thegap 26 expands. The presence of a sizable and expanding air gap 26sometimes prevents deposition of, or causes a rupture in, a continuousconductive layer 12 within the opening 25, which in turn may cause adefect in the conductive connection 14. This is because the conductivelayer 12 is typically formed by first depositing a seeding layer forsubsequent conductor formation. When part of the seeding layer ismissing, a void is formed in both the seeding layer and the conductorwhich is formed above it. Further, the lack of a continuous conductivelayer 12 may create a higher resistance in the ultimately formedconductive connection 14.

One approach at alleviating this disadvantage is to utilize a differentconductive material for the conductive layer 12. Whereas aluminum orcopper generally have been used for the conductive layer 12 (FIG. 2),titanium, titanium nitride or tungsten may be used in a conductive layer112 of a conductive connection 114 (FIG. 3) of a semiconductor device100. While the use of such materials tends to pinch off the size of anair gap 126 formed in an offset opening 125, in instances where theoffset is relatively large, the conductive layer 112 still may not beformed as desired, thus creating the problems noted above. Further,titanium, titanium nitride and tungsten all have a higher electricalresistance than aluminum and copper within the ultimately formedconductive connection, which may create other problems.

There thus exists a need for a fabricated semiconductor device whichdoes not tend to form the offset gap shown in FIG. 2.

SUMMARY OF THE INVENTION

The present invention avoids the offset gap shown in FIG. 2 bypreventing any part of the via 21 from being etched along side of theplug M₁. This is accomplished by fabricating a structure in which aconductive connector comprises a conductive plug positioned within aninsulator and provided on a substrate connection region, an etch-stoplayer deposited on the insulator and around the conductive plug, anintermediate non-conductive layer having an etched via over the plug, afirst conductive layer deposited in and in contact with the etched viaand having a portion in contact with the conductive plug, and a secondconductive layer deposited over the first conductive layer. The etchstep layer prevents the via from being etched along the side of the plugduring via formation.

According to another aspect of the present invention, a memory deviceincluding at least one memory cell may be provided with the justdescribed conductive connector.

The present invention also relates to a method of making a semiconductorconductive connector. The method includes providing a first layer ofdielectric material on an integrated circuit substrate, forming aconductive plug within the first dielectric material, providing anetch-stop layer over the first dielectric layer and around theconductive plug, providing a second layer of dielectric material overthe conductive plug and etch-stop layer, etching the second layer ofdielectric material to the conductive plug and etch-stop layer to form avia, and forming a conductive connector in the via in contact with theconductive plug.

These and other advantages and features of the invention will be morereadily understood from the following detailed description which isprovided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an idealized cross-sectional view of a conventionallyfabricated conductor connection in a semiconductor device.

FIG. 2 is a cross-sectional view like FIG. 1 showing an offset via.

FIG. 3 is a cross-sectional view like FIG. 2 showing another offset via.

FIG. 4 is a cross-sectional view of a semiconductor device constructedin accordance with an embodiment of the present invention.

FIG. 5 is a cross-sectional view of a semiconductor device constructedin accordance with another embodiment of the present invention.

FIG. 6 illustrates a method of making the device shown in FIG. 5.

FIG. 7 illustrates a method of making semiconductor products inaccordance with an embodiment of the present invention.

FIG. 8 illustrates a processor-based system constructed in accordancewith an embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Referring now to the drawings, where like numerals designate likeelements, there is shown in FIG. 4 a semiconductor device 200 with asubstrate 24 and a conductive connection 214 that may be formed byeither the single Damascene or double Damascene methods. The substrate24 can be made of any material typically used as a substrate inintegrated circuit fabrication. The conductive connection 214 includesthe first and second conductive layers 12, 16. The conductive layers 12,16 may be formed of one or more of aluminum, copper, doped polysilicate,tantalum, tantalum nitride, titanium, titanium nitride and tungsten. Thesemiconductor device 200 includes the material 20 surrounding the via21. The metal plug M₁ is embedded within a first insulator layer 230,for example, a BPSG layer, and a hard mask layer 228. The hard masklayer 228 may be formed of any material capable of withstanding thesubsequent etching process described below, such as, for example,silicon nitride, silicon carbide, silicon dioxide, or BLOK® (a mixtureof silicon nitride and silicon carbide).

If the hard mask 228 is formed of, for example, silicon nitride, aplasma etch using CF₄ or C₂F₆ as the etching gas may be utilized to formthe via 21. When either of these etching gases reacts with the BPSGmaterial 20, the oxygen contained within the material 20 is released andwill react with the carbon in the etching gas to form carbon dioxide anddesorb. However, when the etching gas reacts with the silicon nitride,there is no oxygen in the film, so a polymer containing carbon isformed. The polymer slows down or stops the etch of the silicon nitride,particularly, when the carbon to flourine ratio is high.

The result of this etching process is that etching of the insulatinglayer 20 to form the via 21 will stop at the hard mask 228 and theformation of an offset opening like the offset openings 25, 125 shown inFIGS. 2 and 3 will be prevented. Accordingly, as shown in FIG. 4, thevia 21 etching stops at the top surface of the conductive plug M₁ andmask 228. The layers 12, 16 can then be fabricated in the via 21 and theconductive connection 214 can be used to connect the doped region 22 toother portions of the partially illustrated semiconductor device 200.

Next, a method of forming the conductive connection 214 (FIG. 4) will bedescribed with reference to FIG. 7. At step 400, the insulator layer 230and the hard mask 228 are deposited on the substrate 24 containing thedoped region 22. The doped region 22 may be formed by way of an ionimplant. Further, the doped region 22 may serve as an active region in amemory cell, such as cell 513 (described below). It should be noted thatthe doped region 22 is merely illustrative of just one point on asubstrate where an electrical connection is needed. The conductiveconnection 214 can be fabricated wherever a conductive path is needed.An opening is formed in the insulator 230 and the hard mask 228 layersat step 405. The opening is preferably formed through the use of aphotoresist and masking, followed by one or more anisotropic etchingsteps. The opening alternatively may be formed through mechanical orlaser drilling. After stripping the photoresist, conductive material,e.g., polysilicon, is deposited over the insulator 230, including in theopening, and is chemical-mechanical polished (CMP) to form theconductive plug M₁ at step 410. The planarizing process causes the topsurface of the etch-resistant layer 228 to be co-planar with the topsurface of the conductive element M_(1.)

An insulating layer 20, e.g. BPSG, is then deposited on the insulator230 (step 415) and the via 21 is subsequently etched into the insulatinglayer 20 (step 420). The etching of via 21 is preferably accomplished bylaying a photoresist over the material 20, exposing and developing thephtotoresist to mask a portion of the material 20 that is not to beetched, and then etching the via 21 in the unmasked region. As noted,the hard mask 228 is formed of a material which is relatively resistantto the etching chemistry, and hence acts as an etch stop so there islittle or no etching below the top level of the conductive plug M₁. Thefirst conductive layer 12 is then deposited at step 425 and the secondconductive layer 16 is deposited on the first conductive layer 12 atstep 430, thereby creating the conductive connection 214.

FIG. 5 shows a multi-step semiconductor device 300 having a conductiveconnection 314. The multi-step semiconductor device 300 has a greaterconductive surface area which can be used to form container capacitors,useful, for example, in a memory device. A via 121 is etched above themetallic plug M₁ in several steps to create via portions 122 and 123.The via portion 123 has a greater diameter than the via portion 122,allowing the deposition of more area of first and second conductivelayers 112 and 116. If capacitors are formed in the FIG. 5 via portions122 and 123, then the conductive layer 112 is replaced by a three layerstructure formed of a conductor layer, a dielectric layer, and anotherconductive layer, as is known in the art.

Referring now to FIGS. 6 and 7, to form the semiconductor device 300(FIG. 5), the via 121 is etched in several steps to form the viaportions 122 and 123. Specifically, a layer of the material 120 isdeposited over the hard mask 228 and the plug M₁ (step 410). Afterlaying down a photoresist 130 and a mask 132, photoresist 130 ispartially developed, and the developed portions and the mask 132 areremoved and the remaining photoresist 130 is stripped. The via portion122 is then etched at step 415. A second layer of photoresist 130 isthen deposited. A second mask 134 is utilized to develop a portion ofthe second photoresist layer 130. The developed portion is removed asdescribed above. Further the mask 134 is removed and the remainingphotoresist 130 is stripped. The via portion 123 is then etched at step435. After the via portions 122, 123 have been formed, and thephotoresist 130 and mask 134 have been removed, layers 112, 116 (whichare similar to the layers 12, 16, respectively) are deposited in the via121 (steps 425, 430).

Referring now to FIG. 8, a device constructed in accordance with theinvention can be used in a memory circuit, such as a DRAM device 512, orother electronic integrated circuit, within a processor-based system500. The processor-based system 500 may be a computer system, a processcontrol system or any other system employing a processor and associatedmemory. The system 500 includes a central processing unit (CPU) 502,which may be a microprocessor. The CPU 502 communicates with the DRAMdevice 512, which has cells 513 that include the semiconductor device200 (or the semiconductor device 300), over a bus 516. The CPU 502further communicates with one or more I/O devices 508, 510 over the bus516. Although illustrated as a single bus, the bus 516 may be a seriesof buses and bridges commonly used in a processor-based system. Furthercomponents of the system 500 may include a read only memory (ROM) device514 and peripheral devices such as a floppy disk drive 504, and CD-ROMdrive 506. The floppy disk drive 504 and CD-ROM drive 506 communicatewith the CPU 502 over the bus 516.

The present invention provides a semiconductor device which does notsuffer from the aforementioned disadvantages caused by an etched area tothe side of the conductive plug M₁. The present invention furtherprovides a method for making semiconductor devices without forming airgaps in trenches offset from a conductive plug.

While the invention has been described in detail in connection withpreferred embodiments known at the time, it should be readily understoodthat the invention is not limited to such disclosed embodiments. Rather,the invention can be modified to incorporate any number of variations,alterations, substitutions or equivalent arrangements not heretoforedescribed, but which are commensurate with the spirit and scope of theinvention. Accordingly, the invention is not to be seen as limited bythe foregoing description, but is only limited by the scope of theappended claims.

What is claimed as new and desired to be protected by Letters Patent ofthe United States is:

1-38. (canceled)
 39. A semiconductor device comprising: an insulatorlayer; a conductive plug positioned within said insulator layer andformed of a single conductive material; a doped region connected to saidconductive plug; a non-conductive layer having an etched via formed atleast partially over said conductive plug, wherein a first portion ofsaid etched via is wider in diameter than said conductive plug; and aconductive connector formed in said via in electrical contact with saidplug and including a first conductive layer deposited in and in contactwith said etched via and a second conductive layer deposited over and incontact with said first conductive layer, said first conductive layerincluding a portion in contact with said conductive plug.
 40. Thesemiconductor structure of claim 39, further comprising an etch-stoplayer located on said insulator layer and surrounding said plug.
 41. Thesemiconductor structure of claim 40, further comprising an wherein saidetch-stop layer comprises silicon nitride.
 42. The semiconductorstructure of claim 40, wherein said etch-stop layer comprises siliconcarbide.
 43. The semiconductor structure of claim 40, wherein saidetch-stop layer comprises silicon dioxide.
 44. The semiconductorstructure of claim 40, wherein said etch-stop layer comprises siliconnitride and silicon carbide.
 45. The semiconductor structure of claim40, wherein said non-conductive layer comprises doped silicate glass.46. The semiconductor structure of claim 45, wherein said doped silicateglass comprises borophosphosilicate glass.
 47. The semiconductorstructure of claim 40, wherein said first conductive layer comprises oneor more materials selected from the group consisting of aluminum,copper, doped polysilicate, tantalum, tantalum nitride, titanium,titanium nitride and tungsten.
 48. The semiconductor structure of claim40, further comprising a substrate with a connection region, whereinsaid conductive plug is provided over said connection region.
 49. Asemiconductor device comprising: at least one memory cell comprising: anactive region in a substrate; a conductive plug formed of a singleconductive material positioned within an insulator layer and providedover said active region, said conductive plug being electricallyconnected with said active region; an intermediate non-conductive layerprovided over said insulator layer having an etched via over said plug,said etched via having a first via portion wider in diameter than saidconductive plug, and a second via portion above said first via portionhaving a greater diameter than said first via portion; and a firstconductive layer deposited in and in contact with said first and secondvia portions, said first conductive layer including a portion in contactwith said conductive plug, and a second conductive layer deposited overand in contact with said first conductive layer.
 50. The semiconductormemory device of claim 49, wherein said intermediate layer comprisesdoped silicate glass.
 51. The semiconductor memory device of claim 50,wherein said doped silicate glass comprises borophosphosilicate glass.52. The semiconductor memory device of claim 49, wherein said firstconductive layer comprises one or more materials selected from the groupconsisting of aluminum, copper, doped polysilicate, tantalum, tantalumnitride, titanium, titanium nitride and tungsten.
 53. The semiconductormemory device of claim 49, wherein said second conductive layercomprises one or more materials selected from the group consisting ofaluminum, copper, doped polysilicate, tantalum, tantalum nitride,titanium, titanium nitride and tungsten.
 54. The semiconductor memorydevice of claim 49, further comprising a plurality of said memory cells.55. The semiconductor memory device of claim 54, wherein said pluralityof said memory cells are in an array.
 56. A processor-based systemcomprising: a processing unit; a semiconductor circuit coupled to saidprocessing unit, said semiconductor circuit comprising: a conductiveplug formed of a single conductive material positioned within aninsulator and provided on a connection region; an intermediatenon-conductive layer provided over said insulator having at least anetched via over said conductive plug, said etched via having a first viaportion being wider in diameter than said conductive plug, and a secondvia portion above said first via portion having a greater diameter thansaid first via portion; and a conductive connector electrically coupledto said connection region, said conductive connector comprising a firstconductive layer deposited in and in contact with said first and secondvia portions, said first conductive layer including a portion in contactwith said conductive plug, and a second conductive layer deposited overand in contact with said first conductive layer.
 57. The processor-basedsystem of claim 56, wherein said connection region comprises a dopedregion within said substrate.
 58. The processor-based system of claim56, wherein said intermediate layer comprises doped silicate glass. 59.The processor-based system of claim 58, wherein said doped silicateglass comprises borophosphosilicate glass.
 60. The processor-basedsystem of claim 56, wherein said first conductive layer comprises atleast one layer of one or more materials selected from the groupconsisting of aluminum, copper, doped polysilicate, tantalum, tantalumnitride, titanium, titanium nitride and tungsten.
 61. Theprocessor-based system of claim 56, wherein said second conductive layercomprises at least one layer of one or more materials selected from thegroup consisting of aluminum, copper, doped polysilicate, tantalum,tantalum nitride, titanium, titanium nitride and tungsten.
 62. Theprocessor-based system of claim 56, further comprising a substrate, andwherein said connection region is located in said substrate, and whereinsaid conductive plug is located over said connection region.
 63. Amethod of making a semiconductor device, said method comprising: forminga layer of insulating material over a substrate; forming a conductiveplug within said first layer of insulating material, wherein saidconductive plug consists essentially of a single conductive material;forming a second layer of insulating material over said conductive plug;and etching said second layer of insulating material to said conductiveplug and etch-stop layer to form a via having first and second viaportions, wherein said first via portion is wider than the conductiveplug's width, and said second via portion is wider than said first viaportion.
 64. The method of claim 63, further comprising depositing atleast a first conductive layer in said first and second via portions.65. The method of claim 64, comprising depositing a second conductivelayer over said first conductive layer in said first and second viaportions.
 66. The method of claim 63, wherein said plug is formed by:forming an opening in said first layer of insulating material;depositing a conductive material on said first layer of insulatingmaterial, filling said opening; and abrading said conductive materialfrom the top surface of said first layer of insulating such that onlyconductive material within said opening remains.
 67. The method of claim66, wherein said abrading comprises chemical-mechanical polishing ofsaid conductive material.
 68. The method of claim 66, wherein saidconductive plug is connected to a doped region in said substrate.
 69. Amethod of making a semiconductor device, said method comprising: forminga first non-conductive layer over a substrate; forming a conductive plugwithin said first non-conductive layer, wherein said conductive plugconsists essentially of a single conductive material; forming a secondnon-conductive layer over said conductive plug; forming a via havingfirst and second via portions by etching said second non-conductivelayer to said conductive plug and etch-stop layer, wherein said firstvia portion is wider in diameter than said conductive plug; anddepositing a conductive material within said first and second viaportions.
 70. A method of making a semiconductor device, said methodcomprising: forming an active region in a semiconductor substrate;forming a first insulator layer over said active region; forming asingle conductive material within said first insulator layer, whereinsaid conductive material is electrically connected with said activeregion; forming a second insulator layer over said conductive material;forming a via having first and second via portions within said secondinsulator layer, wherein said first via portion is wider in diameterthan said conductive material, and wherein said second via portion iswider in diameter than said first via portion; and forming a conductiveconnector in said first and second via portions that are in electricalcontact with said conductive material.